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Research report 445 Investigating the contribution of sealing chip application rates to the early failure of chipseals

Published: | Category: Activity management , Research programme , Research & reports | Audience: General

Chipsealing is the predominant resurfacing used on the state highway network in New Zealand. An important component of chipseals is the sealing chip layer that is applied to protect the binder layer and provide surface texture and surface friction. There are a number of specifications written to ensure that the sealing chip used is the correct size and shape, and that it has the appropriate ‘polished stone value’ (PSV), but no specifications on chip application rates exist. Early-life failures of chipseals are generally attributed to the binder, the binder application rate, or the weather; however, the sealing chip application rate may also contribute significantly to these early failures.

The objectives of this research, which was carried out between July 2006 and December 2009, were to:

  1. determine the effect of variations in chip application rate by constructing several seals with varied chip application rates, and monitoring the performance of the seals for two years
  2. assess the effect of the time of sealing (in terms of season and weather) with chip application rates and the success rate of the chipseals
  3. develop a pictorial and quantitative guideline for the correct application rate for sealing chip in New Zealand.

This report documents the performance, over the first two years after construction, of chipseals that were constructed using different chip application rates.

Publication details

  • Author:
  • Published: July 2011
  • Reference: 445
  • ISBN/ISSN: ISBN 978-0-478-38000-0 (electronic)
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